Verilog non-blocking vs blocking assignments

1.non-blocking assignments.

module add(a, b, y, sel, clk); input a, b; output y; input sel; input clk; reg y; reg k; always @(posedge clk)begin    if(sel == 0)begin        k <= a;        y <= k;     end     else if(sel == 1)begin        k <= b;        y <= k;     end     else      y <= 1'b0; end endmodule

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2.blocking assignments.

module add(a, b, y, sel, clk); input a, b; output y; input sel; input clk; reg y; reg k; always @(posedge clk)begin    if(sel == 0)begin        k = a;        y = k;     end     else if(sel == 1)begin        k = b;        y = k;     end     else      y = 1'b0; end endmodule